CS701 - High Performance Computing, July-Dec, 2014

Welcome to the CS701 - High Performance Computing course page.

Course Objectives

  • Identify the trade-offs involved in designing a multiprocessor to improve the execution time of our programs.

Course Syllabus

Definition, RISC ISA, RISC Pipeline, Performance Quantification. Instruction Level Parallelism - Pipeline Hazards, Combating hazards, Scheduling, Branch Prediction, Superscalar Processors, Out-of- Order execution. Memory hierarchy. VLIW, Vector Processors. Data Parallelism – GPU. Interconnection Networks. Topics of current research.

Course Evaluation

Assignments - 15%, Course Project 25%, Mid Sem - 20%, Final Exam - 40%.

Reference Material

Reference Books/Textbooks:

  • John Hennessy and David Patterson. Computer Architecture - A Quantitative Approach. 5ed. Morgan Kaufmann.
  • John P. Shen and Mikko H. Lipasti. Modern Processor Design - Fundamentals of Superscalar Processors. Tata McGraw Hill.

Other References, Course supplements:

  • Guest lectures.

Class Lectures/Assignments

Course Project

Guest Lectures

Date Speaker Title/PDF
August 2 Dr. Janakiraman V, IBM Pvt. Ltd. C Programming and the Assembly Language.

Paper Reading Suggestions

Processor Microarchitectures

  • R. E. Kessler, E. J. McLellan and D. A. Webb, The Alpha 21264 Microprocessor Architecture. ICCD '98.
  • Anderson, Sporacio, Tomasulo, "The IBM System/360 Model 91: Machine Philosophy and Instruction Handling", Jan 1967, IBM Journal.
  • Hinton et. al., The microarchitecture of the Pentium 4 Processor, Intel Technology Journal Q1, 2001.
  • Mittal, Peleg and Weiser, "MMX Technology Overview", Intel Technology Journal Q3, 1997.
  • Sharanpani, Arora, Itanium Processor Microarchitecture, IEEE Micro, Sep-Oct, 2000.
  • Kahle et. al., Introduction to the Cell multiprocessor, IBM Journal, Vol. 49, No. 4/5, Jul/Sep, 2005.
  • Sinharoy et. al., POWER5 system microarchitecture, IBM Journal, 2005.
  • Smith and Sohi, The microarchitecture of Superscalar processors, Proc. of the IEEE, Dec. 1995.
  • Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE Micro 1996.

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