IS860 - High Performance Computing for Security, Jan-May, 2014

Welcome to the IS860 - High Performance Computing for Security course page.

Course Objectives

  • Identify the trade-offs involved in designing a multiprocessor to improve the execution time of our programs.

Course Syllabus

Definition, RISC ISA, RISC Pipeline, Performance Quantification. Instruction Level Parallelism - Pipeline Hazards, Combating hazards, Scheduling, Branch Prediction, Superscalar Processors, Out-of- Order execution. Memory hierarchy. VLIW, Vector Processors. Data Parallelism – GPU. Interconnection Networks. Topics of current research.

Course Evaluation

Quiz - 10%, Assignments - 15%, Course Project 15%, Mid Sem - 20%, Final Exam - 40%.

Reference Material

Reference Books/Textbooks:

  • John Hennessy and David Patterson. Computer Architecture - A Quantitative Approach. 5ed. Morgan Kaufmann.
  • John P. Shen and Mikko H. Lipasti. Modern Processor Design - Fundamentals of Superscalar Processors. Tata McGraw Hill.

Reference Papers

  • Kessler, McLellan and Webb, The Alpha 21264 Microprocessor Architecture.
  • Anderson, Sporacio, Tomasulo, "The IBM System/360 Model 91: Machine Philosophy and Instruction Handling", Jan 1967, IBM Journal.
  • Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction", IEEE Transactions on Computers, July 1981.
  • Goodman, Using cache memory to reduce processor-memory traffic, ACM ICCA, Pages 124--131, 1983.
  • Hinton et. al., The microarchitecture of the Pentium 4 Processor, Intel Technology Journal Q1, 2001.
  • Mittal, Peleg and Weiser, "MMX Technology Overview", Intel Technology Journal Q3, 1997.
  • Sharanpani, Arora, Itanium Processor Microarchitecture, IEEE Micro, Sep-Oct, 2000.
  • Kahle et. al., Introduction to the Cell multiprocessor, IBM Journal, Vol. 49, No. 4/5, Jul/Sep, 2005.
  • Kroft, Lockup-free instruction fetch/prefetch cache organization, ISCA, 1981.
  • McFarling, Combining branch predictors, WRL Tech Report, TN-36, June 1993.
  • Pan, So and Rahmeh, Improving the accuracy of dynamic branch prediction using branch correlation, ACM ASPLOS 1992.
  • Sinharoy et. al., POWER5 system microarchitecture, IBM Journal, 2005.
  • Smith and Sohi, The microarchitecture of Superscalar processors, Proc. of the IEEE, Dec. 1995.
  • Tullsen, Eggers and Levy, Simultaneous Multithreading: Maximizing on-chip parallelism, ISCA, 1995.
  • D W Wall, Limits of instruction level parallelism, WRL Technical Note, TN-15, Dec. 1990.
  • Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE Micro 1996.
  • Yeh and Patt, Alternative implementations of two-level adaptive branch prediction, ISCA, 1992.

Class Lectures

Paper Reading and Seminars