Welcome to the CO403--Advanced Microprocessors/IS860--High Performance for Security course page.
On the completion of the course, the student should be able to
- Explore, by simulation, the tradeoffs invovled in inclusion or deletion of a microarchitectural component in a uniprocessor pipeline.
- Determine and contrast the effect of various sizes and associativities of levels of the memory hierarchy on the performance and power of the multicore chip.
- Illustrate and compare different cache coherence protocols and memory consistency models in multiprocessors.
- Compute interconnection network parameters such as latency and power of various topologies in a multiprocessor environment.
- Provide systematic and comprehensive treatment of the components involved in the processor pipeline that extract instruction level parallelism.
- Provide a strong foundation on memory hierarchy design and tradeoffs in both uniprocessor and multiprocessors.
- Illustrate the cache coherence and consistency problems in multiprocessors, and their existing solutions.
- Present the fundamentals of interconnection network design, architecture and implementation in a multiprocessor setting.
Instruction Level Parallelism: Pipelining, Hazards, Compiler techniques for ILP, Branch prediciton, Static and Dynamic Scheduling, Speculation, Limits of ILP. Multicore Memory Hierarchy: Cache tradeoffs, Basic and Advanced optimizations, Virtual Memory, DRAM optimizations. Multiprocessors: Symmetric and Distributed architectures, Cache coherence protocols - Snoopy and Directory based, ISA support for Synchronization, Memory Consistency Models. Interconnection Networks: Architectures, Topologies, Performance, Routing, Flow control, Future of NoCs. VLSI: Transistor Theory. Moore's Law. Delay, Power, Energy, Temperature dependence in integrated circuits.
QTorials, Assignments - 30%, Course Project 10%, Mid Sem - 20%, Final Exam - 40%.
- John Hennessy and David Patterson. Computer Architecture - A Quantitative Approach. 5ed. Morgan Kaufmann.
- John P. Shen and Mikko H. Lipasti. Modern Processor Design - Fundamentals of Superscalar Processors. Tata McGraw Hill.
- William J Dally and Brian Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann. 2004.
- Mark Hill/Margaret Martonosi (eds.). Synthesis Lectures on Computer Architecture, Morgan and Claypool, 2006 -- 2014.
- Jean-Loup Baer. Microprocessor Architecture: From Simple Pipelines to Chip Multiprocessors. Cambridge University Press, 2009.
- Bruce Jacob, Spencer Ng, David Wang. Memory Systems: Cache, DRAM, Elsevier, 2007.
- William Dally and Brian Towles. Principles and Practices of Interconnection Networks, MK, 2004.
|Title, Lecture Notes|
|Technology Trends: Power, Dependability, Performance Quantification, Simulation|
|Pipelining and ILP: MIPS Pipeline, Structural and Data Dependences, Static Scheduling, Exceptions, Control Dependence and Branch Prediction.|
|ILP - Dynamic Scheduling, OoO execution, Speculation: OoO Processors and Dynamic Scheduling, Compiler based Speculation, Hardware based Speculation, BTB, Multithreading.|
|The Memory Hierarchy - Cache, Virtual Memory, DRAM, Advanced Optimizations : Memory Hierarchy Introduction, Caches, Advanced Cache Optimizations, Virtual Memory, DRAM.|
|Multiprocessors: Symmetric and Distributed shared memory processors, Shared memory and Message Passing programming models, Cache coherence, Locks, Consistency Models, Transactional Memory.|
|Duato and Pinkston's Interconnection Networks slides.|
|12th Feb, 2PM, ATB Seminar Hall.||Prof. Y. N. Srikant, IISc, Bangalore||Green Software Development: Energy-aware Compilers and Green Programming|
|13th Feb, 9AM - 12PM, 1.30PM - 3.30PM, CSE Seminar Hall.||Dr. Prakash Raghavendra, AMD, Bangalore||High Performance Computing with GPGPUs|