Welcome to the CO200 - Computer Organization and Architecture page.
- To understand how machine code is executed by a computer.
- To examine the abilities of software to instruct the hardware to perform a desired actions
- To illustrate how the processor instructs a functional unit to perform a desired operation
- To introduce hardware techniques to improve performance of the processor
- To illustrate the memory hierarchy of a modern day processor
- To introduce the salient features of parallel and multi-processing.
- To gain insight into the setting in which our programs execute.
- To improve the setting in which our programs execute - to improve the performance of the system
- M1: Computers and Data: Architecture vs. Organization. Frequency, Processor performance. Representation of information.
- M2: Instruction Set Architecture: Addressing modes. Instruction classes. Handling subroutine calls.
- M3: Processor Datapath: ALU
- M4: Processor Control Unit: Hardwired control. Microprogrammed control CPU design. Examples.
- M5: Pipelining: Pipelining, dependences and hazards.
- M6: Memory Hierarchy: Cache memory, Main memory, Virtual memory.
- M7: Input/Output: Memory mapped I/O, Interrupt driven I/O. DMA. Secondary storage.
- M8: Parallel Processing: Flynn's Classfication. Cache coherence. Warehouse scale computers. Interconnection networks. Parallel programming paradigms
Quizzes + Assignments - 40%, Mid Sem - 20%, Final Exam - 40%.
- D Patterson and J Hennessy, Computer Organization and Design - The Hardware/Software Interface. ARM edition. 4e. Elsevier, 2008.
- Hamacher, Vranesic, Zaky. Computer Organization. 5e. Tata McGraw Hill, 2011.
- J P Hayes, Computer Architecture and Organization, 3e, McGraw Hill, 1998.
- M. Morris Mano. Computer System Architecture. 3e. Pearson. 2007.
- Matthew Jacob - High Performance Computing
- Bhaskaran Raman - Computer Organisation and Architecture
- S. Raman - Computer Organization
- Jatindra Kumar Deka - Computer Organisation and Architecture
|Course Introduction, Architecture vs. Organization|
|Expert Lecture by Prof. Matthew Jacob, CSA, IISc - Moore's Law|
|M1 - Computers and Data|
|M2 - Addressing Modes, MIPS ISA (Also refer the MIPS ISA Reference Sheet), Compilation, Linking. Subroutine Calls.|
|M3 - Processor Basics, Adders, ALU, Multiplication.|
|M4 - Control Unit Design - GCD Hardware, 2's Complement Multiplier.|
|Expert Lectures by Prof. Atal Chaudhari, Jadhavpur University - Pipelining and Memory Hierarchy|
|M5 - Processor Pipeline.|
|M6 - The Memory Hieararchy.|
|M7 - Parallel Processing.|