CO200 - Computer Organization and Architecture, July-Dec, 2016

Welcome to the CO200 - Computer Organization and Architecture page.

Course Objectives

  • To understand how machine code is executed by a computer.
  • To examine the abilities of software to instruct the hardware to perform a desired actions
  • To illustrate how the processor instructs a functional unit to perform a desired operation
  • To introduce hardware techniques to improve performance of the processor
  • To illustrate the memory hierarchy of a modern day processor
  • To introduce the salient features of parallel and multi-processing.

Course Syllabus

Click here for the detailed syllabus.

  • M1: Computers and Data: Architecture vs. Organization. Frequency, Processor performance. Representation of information.
  • M2: Instruction Set Architecture: Addressing modes. Instruction classes. Handling subroutine calls.
  • M3: Processor Datapath: ALU
  • M4: Processor Control Unit: Hardwired control. Microprogrammed control CPU design. Examples.
  • M5: Pipelining: Pipelining, dependences and hazards.
  • M6: Memory Hierarchy: Cache memory, Main memory, Virtual memory.
  • M7: Input/Output: Memory mapped I/O, Interrupt driven I/O. DMA. Secondary storage.
  • M8: Parallel Processing: Flynn's Classfication. Cache coherence. Warehouse scale computers. Interconnection networks. Parallel programming paradigms

Reference Books

  • D Patterson and J Hennessy, Computer Organization and Design - The Hardware/Software Interface. 5e. Elsevier, 2008.
  • David A Patterson and John L Hennessy. Computer Organization and Design – The Hardware/Software Interface. 4e. Elsevier. 2012. (The ARM edition is available in the Library).
  • Hamacher, Vranesic, Zaky, Manjikian. Computer Organization and Embedded Systems. 6e. McGraw Hill, 2012.
  • J P Hayes, Computer Architecture and Organization, 3e, McGraw Hill, 1998.
  • M. Morris Mano. Computer System Architecture. 3e. Pearson. 2007.
  • Reference for some of the assignments – David M. Harris and Sarah L. Harris, Digital Design and Computer Architecture. 2e. Elsevier. 2013.

NPTEL Courses. Matthew Jacob - High Performance Computing, Bhaskaran Raman - Computer Organisation and Architecture, S. Raman - Computer Organization, Jatindra Kumar Deka - Computer Organisation and Architecture.

Course Evaluation

Quizzes, Tutorials, Assignments - 40%, Mid Sem - 20%, Final Exam - 40%.

Assignments/Lab Work

Sl. No. AssignmentSubmission Date
0 A0 MIPS Programming Assignment - A0 is out. August 12, 1159PM.
1 A1 Hardware modules in SystemC. Sept. 18, 1159PM.

Class Lectures