Welcome to my Homepage
I am an Assistant Professor at the Computer Science and Engineering department in the National Institute of Technology Karnataka, Surathkal. I have a PhD from the ECE department at the Indian Institute of Science, Bangalore. My research interests are in Network-on-Chips, Simulation Acceleration and Parallelization. Our group is called SPARK (Systems, Parallelization and Architecture Research at NITK) lab at NITK.
Address: Departmant of CSE, National Institute of Technology Karnataka, Surathkal, Srinivasnagar P. O., Mangalore - 575025. India. Office: +91 824 2473409. Email: , .
Courses: Dec, 2017 - May 2018
- CO200 - Computer Organization and Architecture
- CO316 - Computer Architecture Lab
- CS701 - High Performance Computing
- Khyamling Parane, Prabhu Prasad B M and Basavaraj Talawar, "FLNoC - FPGA based Network-on-Chip framework supporting Low latency router architecture", 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018), Co-located with Embedded Systems Week, October 4 -- 5, 2018 | Torino, Italy.
- Basavaraj Talawar, Pramod Yelmewad. "GPU-based Iterative Hill Climbing Algorithm to Solve Symmetric Salesman Problem.", Book Chapter in "HPC and Big Data: Convergence and Ecosystem", IOS Press, Amsterdam, Book Series "Advances in Parallel Computing."
- Ujjwal Pasupulety, Bheemappa Halavar and Basavaraj Talawar,"Accurate Power and Latency Analysis of a Through-Silicon Via (TSV)", 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI'18), 19--22, September, 2018, PES Institute of Technology, South Campus, Bangalore, India.
- Anil Kumar and and Basavaraj Talawar, "Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks", 11th Intl. Conference on Contemporary Computing, IC3 2018, August 2018, Jaypee Institute of Information Technology, Noida, U.P., India.
- Bheemappa Halavar and Basavaraj Talawar, "Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-Chip", Intl. Conference on Signal Processing and Communications (SPCOM 2018), 16--19 July, 2018, Indian Institute of Science, Bangalore, India.
- Prabhu Prasad B M, Khyamling Parane and Basavaraj Talawar, "YaNoC: Yet another Network-on-Chip Simulation Acceleration Engine using FPGAs", 31st International Conference on VLSI Design, 2018, Pune, India, Jan 8-10, 2018.